A charge device model (CDM) is a model for characterizing the likelihood of an electronic device being damaged from an electrostatic discharge (ESD), such as by the touching of a contact of an integrated circuit. CDM testing consists of charging a package to a specified voltage, then discharging this voltage through a package lead. The discharge current is limited only by the parasitic impedance and capacitance of the device. Therefore, CDM discharge current can find multiple paths on the die to get out to the package lead. The goal of ESD design is to provide an intended low impedance path with enough routing recourses to handle CDM discharge current, and prevent damage to internal circuits on the die.
However, the discharge of electric charge through parasitic paths, which are often available in conventional devices for discharge in parallel with an intended path, can result in damage to the integrated circuit. These parasitic paths are weaker and are generally the first to fail, leading to an increase of leakage current at the I/O pad. Not only does increased leakage current change the operation of the transistor, but it may also lead to failure of the integrated circuit. Because integrated circuits are implemented in larger systems, the failure of an integrated circuit can lead to the failure of the larger system as a whole. Accordingly, it is beneficial to reduce the effects of electrostatic discharge on integrated circuits.